Verification IP has become a popular mainstay within a chip design verification flow after some clever engineers applied the black box concept to verification. The result is verification engineers having access to previously tested blocks of protocols, interfaces and memories required to verify their SoC designs deployed across thousands of projects.
Bipul Talukdar, SmartDV’s director of applications engineering for North America, will present real-world examples of Verification IP successfully implemented in SoC designs. He will show how it reduces debug time and accelerates the time to tapeout.
