Status of the DARPA CHIPS program

Meet the Experts Theater Tuesday, July 09
11:05am to 11:35am

The explosive growth in mobile and telecommunication markets has pushed the semiconductor industry toward integration of digital, analog, and mixed-signal blocks into system-on-chip (SoC) solutions. Advanced silicon (Si) complementary metal oxide semiconductor (CMOS) technology has enabled this integration, but has also led to a rise in costs associated with design and processing. Driven by aggressive digital CMOS scaling for high-volume products, Intellectual Property (IP) reuse has emerged as a tool to help lower design costs associated with advanced SoCs. The monolithic nature of state-of-the-art SoCs is not always acceptable for DoD or other low-volume applications due to factors such as high initial prototype costs and requirements for alternative material sets. To enhance overall system flexibility and reduce design time for next-generation products, the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program seeks to establish a new paradigm in IP reuse.

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