Panel: Are we Experiencing a Renaissance in Chip Design and EDA?

TechTALK Theater Tuesday, July 09
2:55pm to 4:00pm

Joe Costello
Doug Letcher
Adnan Hamid
Simon Davidmann
Simon Butler

Jim Hogan

Chip Design Tools took off in the late 1980s with the advent of high-performance UNIX 32-bit graphics workstation that enabled a software-only business model as opposed to turnkey systems; the introduction of design compilers and a verification based design methodology, and the ASIC technology which dramatically broadened the world of chip design from a small number of large semiconductor companies to the much bigger world of startups and system companies.

The Chip EDA business changed significantly after 2000 as the cost of chip designs in advanced processes technologies soared leading to fewer chip starts and a situation where once again, only the largest companies with big proven markets could afford to play in chip design. Even the reliable driver of growth, Moore’s law started to slow down. There was a dramatic consolidation in the number of chip companies and EDA companies so support them. Venture money dried up for investment in these segments further accelerating the consolidation.

As we enter the 2020’s, there is a Renaissance of chip design and EDA.  It is being powered by three big macro trends similar to what ushered in the Golden Age 30 years ago:

  1. A new compute platform – infinite scalable compute capacity in the cloud along with cloud native development tools like GitHub and Kubernetes, which enables a new SaaS business model that lets customers purchase exactly the amount of software cycles they need
  2. A customer demand for much higher simulation throughput driven by the increased size and complexity of chip design, coupled with high tape-out costs which means one must have the highest verification coverage to avoid any test escapes
  3. A new chip design opportunity – application or domain specific processors that coupled with the cloud platform will enable startups and system companies to build their own specialized processors rather than the handful of giant companies building the enormously expensive general-purpose processors.

This changing macro environment coupled with a resurgence in chip design starts leads to a new and significant opportunity for EDA tools to support this.

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